Dolly Singh
System-on-Chip Design Engineer at Intel Corporation
- Role
- System-on-chip Design Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Dolly Singh
Overall 3+ years of experience in logical equivalence and low power analysis, designverification, UPF, simulation model development of various SoC blocks, and development ofSoC solutions.
Experience
System-on-chip Design Engineer
Jul 2020 — Present · Bengaluru, IN
Key involvement in signing off checks for formal verification at SOC partition andsubsystem level, ensuring there is the functionality check between RTL and netlistDiligent in signing off LEC for 50+ partition for server chipPerforming paranoia runs- sequential, removing scan and ctech for all the 50+partitionsReviewing various audits and other reports at partition and SOC levelExecuting the net to net & RTL to RTL LEC runs for project technical requirementphaseInteracting closely with different cross functional teams including RTL team, DFT teamand Physical design teamPerforming low power checks (VCLP) at partition level Successful in working on power aware simulations for 20+ blocks
Education
National Institute of Technology Durgapur
Master of Technology - MTech, VLSI
2018 — 2020
Delhi University
Bachelor of Technology (B.Tech.), Electronics science
2013 — 2017
Skills
- C++
- Customer Service
- Powerpoint
- Microsoft Excel
- Windows
- Matlab
- English
- Microsoft Office
- Teamwork
- C
- Photoshop
- Research
- Microsoft Word
- Public Speaking
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