Dmitry Sidorov
Compiler Engineer @Intel
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WORK HISTORY
Compiler Engineer @Intel
I\'m working as computer engineer in DPC++ compiler for oneAPI project.\\\\n\\\\nI initially worked on FPGA features across the full compilation stack from clang front end to FPGA emulator\'s backend, including DPC++ high-level runtime and FPGA emulator\'s lower level runtime.\\\\nNotable features that I implemented for FPGA in DPC++ compiler: pipes, buffer location, function and loop attributes. I was a code owner of FPGA features in https://github.com/intel/llvm providing technical assistance to other team members.\\\\n\\\\nNow I\'m working mostly on SPIR-V component. My responsibilities are: team\'s grow in expertise in SPIR-V, designing complex features, providing technical assistance and expertise. Despite that still manage to actively write code :)\\\\n\\\\nAs one of two https://github.com/KhronosGroup/SPIRV-LLVM-Translator maintainers (within SPIR Khronos team) I\'m also providing communications with non-Intel community of the translator. I\'m author of NonSemantic.Shader.DebugInfo.200 extension that provide debug capabilities for heterogeneous language models (including DPC++, OpenMP and Fortran through OpenMP offloading), which stands out for its Fortran support, co-author of SPV_INTEL_joint_matrix and contributor to SPV_KHR_cooperative_matrix extensions that adds AMX instructions representation in SPIR-V. Overall I\'m author and co-author of more than 10 SPIR-V extensions and a code owner of LLVM IR to SPIR-V translator in https://github.com/intel/llvm.\\\\n \\\\n\\\\n \\\\n \\\\n\\\\n \\\\n
EDUCATION
Nizhny Novgorod State University
Master's degree
Nizhny Novgorod State University
Bachelor's degree
ABOUT DMITRY SIDOROV
Enthusiastic in heterogeneous and HPC programming models. I\'m working as compiler…
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