Dixit Soni

About Dixit Soni

17+ Years of experience in, 1. Coverage and Requirements Driven Verification Methodology.2. Designing of Monitors and Checkers using System Verilog Assertions and coverage.3. Writing Assertions using System Verilog, PSL languages.4. Writing timing assertions for some standard interfaces like SPI and LIN.5. Constraint Randomization using SystemC and System Verilog.6. Developing Perl scripts for regression and various other automation tasks.7. Code Coverage and Functional Coverage analysis by using the tools like VCS, Questasim and NCsim.8. Product Validation like SVA and PSL features support in EDA tool.9. DDR2 - SDRAM generic model development with gui.10. Soc level testing of D4DP chip.11. VE development and testing of Display Port TX IP.12 DDR2 – SDRAM generic GUI application development.13 FPGA Soc verification.14 LDPC verification of Controller.15. PCIe Gen4 IP verification.16. PCIe bridge unit verification17. Modem SS/SoC verification18. AI/IOTG based SoC validation19.Client and Server SS/SoC level verification and project management20.Owned and delivered HSIO SS having dual mode PCIe Gen4 controller and SATAe controller for multiple ARM based SoCs21.Delivered NPU(Neural processing unit) SS for inferencing and data acceleration for multiple x86 and ARM based SoCs22.Lead DV team of total 25 members to deliver multiple IP/SS.Goal : To be a successful team player with hard work, dedication and integrity, and to gain as much practical knowledge as possible by working in a learning organization so as to enhance my skills and add value to the organization.Specialties:(1) Scripting Languages : Worked on Shell scripting and Perl Scripting(2) Operating Systems : Windows98-ME-XP, Linux(3) Programming Languages : C, C++(4) HDL/HVL Languages : Verilog, System Verilog, VHDL(5) Protocols : PPC, SPI,LIN, NAND Flash, DDR2 - SDRAM, DP, PCIe(6) Methodologies : OVM, UVM, Good knowledge of VMM and AVM.(7) EDA Tools : NC Verilog, Questa-6.3, Questa-6.5c, VERILOG –XL, IUS62_s003, IUS82_s007 of the Cadence (8) DO254 Process based Tools : PREP,DOORS(9) GUI Tools : Incisive Imanager,ICCR, Questasim 6.3h, Questasim 6.5c

Experience

1. Senior Manager Silicon Design Engineering

   AMD

   Jul 2025 — Present

Education

• L.D. College of Engineering

  B.E., Electronics & Communication

  2004 — 2008

Skills

• Soc
• Systemverilog
• Uvm
• Functional Verification
• Systemc
• Vhdl
• Ncsim
• Perl
• Eda
• Spi
• Fpga
• Asic
• Veritas Cluster Server
• Verilog
• Vmm
• Open Verification Methodology