Divya S
Experience in IP Design Verification
- Role
- Senior Design Verification Engineer at Infineon Technologies
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Divya S
Summary of my professional experience:• Solid understanding of the verification flow for ASICs. • Strong programming skills in SystemVerilog and Verilog Hardware Description Languages and UVM verification methodologies. • Having an adequate understanding of HVL concepts is required. Using existing test plans, code test scenarios. Debugging HVL environments and HVL test bench components • Hands-on experience in IP VerificationProtocol Knowledge:UART, MIPI I3C, AHB, AXI.
Experience
Senior Design Verification Engineer
Feb 2023 — Present · Bengaluru, IN
Education
Harcourt Butler Technical University (HBTU), Kanpur
Master of Technology - MTech
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