Divya Sri Battineni
Vlsi Design Engineer @S&C Electric Company
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WORK HISTORY
Vlsi Design Engineer @S&C Electric Company
IL, US
Worked on Low-Power FPGA-Based Controller for Power Distribution Automation, collaborating with cross-functional teams duringrequirements gathering sessions to define precise functional and power targets, achieving over 95% requirement coverage.• Developed energy-efficient FPGA architecture using Verilog/SystemVerilog, incorporating power gating and multi-clock domainmanagement, resulting in a 30% reduction in dynamic power consumption compared to legacy designs.• Performed RTL coding, synthesis using Synopsys Design Compiler, and static timing analysis with PrimeTime, ensuring 98% timingclosure and optimizing the design to meet low-power constraints.• Led prototype deployment on Xilinx FPGA platforms, executing functional validation and real-time field testing in power gridenvironments, achieving 99% functional accuracy and robustness under varied electrical load conditions.• Documented comprehensive power analysis and optimization reports using PowerArtist and PrimePower tools; delivered designvalidation results and improvement recommendations, facilitating 25% faster design iteration cycles.
EDUCATION
Illinois Institute of Technology
Master's degree
R.V.R. & J.C. College of Engineering
Bachelor of Technology - BTech
ABOUT DIVYA SRI BATTINENI
I am a VLSI Design Engineer with experience in ASIC and FPGA design, RTL coding, synthesis, verification, and low-power optimization. My focus is on creating efficient, reliable, and high-performance semiconductor solutions that meet demanding technical requirements while reducing power and improving scalability. I’ve worked across the full design cycle — from gathering requirements and defining architecture to RTL development, functional verification, timing closure, and post-silicon validation. Along the way, I’ve gained hands-on expertise with tools such as Synopsys Design Compiler, PrimeTime, VCS, Cadence Genus, Virtuoso, Voltus, and Xilinx Vivado, and programming in Verilog, SystemVerilog, VHDL, Python, C/C++, and MATLAB. Some career highlights I’m proud of: Designed a low-power FPGA-based controller that reduced dynamic power by 30% while achieving 98% timing closure. Developed a custom ASIC for medical imaging, cutting power by 25% and improving noise performance by 15%, enabling clearer and more accurate results. Resolved 95% of post-silicon test issues through close collaboration with QA and system teams, ensuring robust performance in real-world conditions. Consistently delivered projects with 95%+ requirement coverage and strong cross-functional collaboration. I am currently pursuing my Master’s in VLSI and Microelectronics at Illinois Institute of Technology (Chicago), building deeper expertise in SoC architectures, advanced chip design, and low-power methodologies. I’m passionate about solving complex hardware challenges and driving innovation in semiconductors, healthcare technology, and energy systems. I enjoy connecting with professionals who share an interest in ASIC/FPGA design, verification, and low-power architecture — and I’m open to exploring new opportunities where I can make an impact.
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