Divya Sardana

About Divya Sardana

Digital Design, RTL/ VLSI Design and Verification.Programming: Verilog, System Verilog, UVM, C/C++, Python, Embedded CResearch Interests: Digital Design and VerificationCourses: ASIC Design and Verification, VLSI Design, UVM, Digital Electronics, Electronic System Level and Physical Design, Computer Design and Architecture, GPU ArchitectureWork Experience: Logic Verification of next-generation Edge Routers. PCIe and Host Interface verification.Personal Traits: Great communicator, Quick learner, Curious person with strong conceptual knowledge

Experience

1. Soc Design Engineer

   Intel

   Mar 2020 — Present · Hudson, MA, US

   Responsible for DFT (design-for-test), DFD (design-for-debug) and SOC integration techniques for Scan chains in the company IP Responsible for Subsystem Scan DFT bringup and integration into SoCKey member of the team responsible for end to end Pre Silicon Core Power Management validation of Intel\'s Xeon SoC using emulationExperienced with test-plan creation and execution of core C-states, Legacy and Hardware P-states corner casesExperienced with thermal Power Management testing and debuggingSuccessfully Taped-out 2 Xeon SoC

Education

• North Carolina State University

  Master's degree, Computer Engineering

  2016 — 2018

Skills

• Application-Specific Integrated Circuits (Asic)
• Microsoft Office
• Asic Design
• Microsoft Powerpoint
• Microsoft Excel
• Sql
• Gsm
• Analog Electronics
• Matlab
• Vhdl
• Verilog
• Python
• Network Engineering
• Telecommunications
• Universal Verification Methodology (Uvm)
• C++
• C
• System Verification
• System Verilog
• Very-Large-Scale Integration (Vlsi)
• Microsoft Word
• Cadence Virtuoso
• Physical Design