Divya Nandihalli
- Role
- Asic Design Engineer at Apple
- Location
- Bengaluru, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Divya Nandihalli
I am working as Pixel IP Design Engineer at Apple. Main areas of interest are RTL Design…
Experience
Asic Design Engineer
Sep 2022 — Present
Education
National Institute of Technology Karnataka
Bachelor of Technology - BTech, Electronics and Communications Engineering
University of Southern California
Master of Science (M.S.), VLSI Design
2016 — 2018
National Institute of Technology Karnataka
Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering
2010 — 2014
Skills
- Systemverilog
- Programming
- Simulations
- Microsoft Office
- C
- Rtl Design
- Cadence Encounter
- Vhdl
- Perl
- Matlab
- Java
- Python
- Verilog
- Xilinx Ise
- Modelsim
- C++
- Very-Large-Scale Integration (Vlsi)
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