Divya Khanduri
Design Engineer| SoC Design | Verilog | System Verilog | RTL Design | VLSI | Altera|Intel | M.Tech NIT Kurukshetra
- Role
- Soc Design Engineer at Altera
- Location
- Bareilly, UP, IN
- LinkedIn followers
- 500 followers
About Divya Khanduri
An aspiring professional with proven track record in System Validation Design, NOC Validation(HNOC/uNOC). Well Versed in NOC architecture, facilitating effective contribution to system design and integration processes. I am experienced in hardware and software debugging, validation. I have collaborated with other engineers, designers, and technicians to ensure designs meet specifications. Monitor project timelines and manage resources to ensure timely completion of projects. I am passion for ensuring the functionality and correctness of digital designs. I am ardent about learning new technologies and best practices and delivering high-quality system design that meet the expectations and needs of the clients and users. I am excited to continue leveraging my skills and expertise to drive impactful results in the dynamic and fast-paced industry.Eager to collaborate and drive excellence, I am open to opportunities that challenge and expand my expertise while contributing to the technological landscape.Let’s connect and explore opportunities where my expertise in System on a Chip (SoC) Designing can contribute to driving excellence and achieving remarkable results.Please feel free to reach out to me at d••••••••@gmail.com.
Experience
Soc Design Engineer
Nov 2024 — Present · Bengaluru, IN
As a SOC Design Engineer,I was responsible for Integrating multiple IP\'s of subsystems at SOC level, ensuring efficient connectivity and performance.
Education
National Institute of Technology Kurukshetra
Master of Technology - MTech
2021 — 2023
Bipin Tripathi Kumaon Institute Of Technology
Bachelor of Technology - BTech
2016 — 2020
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