Divya Dandekar
Design Verification Engineer @Cirrus Logic | EX-intern @Intel - Pre Silicon SoC Validation | Electrical Computer Engineering | Portland State University
- Role
- Design Verification Engineer at Cirrus Logic
- Location
- Portland, OR, US
- LinkedIn followers
- 500 followers
About Divya Dandekar
Graduate Student at Portland State University. Aspiring for Design Verification and Validation. As a part of my coursework in my Masters, I gained knowledge in Microprocessor System Design, Introduction to System Verilog, Verilog, and EDA tools like Mentor Questa, Questa Sim, and also Synopsys design Complier.Currently, I am actively seeking internship opportunities for Design Verification Engineer roles to make valuable contributions to the company.
Experience
Design Verification Engineer
Jul 2023 — Present · Austin, TX, US
Formal Verification
Education
Government Polytechnic Nagpur
Diploma in Engineering, Electronics and Telecommunication
2015 — 2018
Portland State University
Master's degree, Electrical and Electronics Engineering
Yeshwantrao Chavan College of Engineering - YCCE
Bachelor of Engineering - BE, Electronics and Telecommunication
2018 — 2021
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