Dishant Tomar

About Dishant Tomar

With a robust foundation in VLSI from National Institute of Technology Surathkal, my 5+ years of journey as a Physical Design Engineer at Cadence Design Systems has been marked by deep engagement with ASIC. Expertise in end to end physical design tasks starting from Flow setup, Power grid implementation, Place & Route, CTS (Clock Tree Synthesis), Layout extraction, STA (Static Timing Analysis), EMIR sign-off & IR-drop Analysis, and delivery of IPs. Good at timing analysis & debugging the various P&R issues for Full chip designs.Recognized for excellence with the DIP Excellence Awards, my role involves leveraging technical competencies to drive innovation. The collaboration with my team has contributed significantly to developing application-specific solutions, empowering us to meet intricate design challenges and maintain Cadence\'s industry leadership.At the moment I\'m working as Lead Physical Design Engineer handling low power and mixed signal designs.

Experience

1. Lead Design Engineer

   Cadence

   Jul 2022 — Present · Bengaluru, IN

   Led physical design tasks for latest technology nodes including TSMC- 3nm, 5nm, 7nm, 12nm, 16nm; Samsung- 5nm, 4nm; ST- 28nm, delivering IPs like PCIe Gen- 1/2/3/4/5/6 and UCIe.• Expert in handling multiple issues in low power & mixed signal designs, ensuring efficient physical verification of IC layout.• My experience in full chip floor-planning, PnR, timing closure, and scripting with Tcl & Perl has been instrumental in achieving project success.

Education

• National Institute of Technology Karnataka

  Master of Technology - MTech

  2017 — 2019