Dipto Thakurta
Sr. Principal Engineer at Intel Corporation
- Role
- Sr Principal Engineer, Test Chip Engineering Group, Technology Design Enablement at Intel
- Location
- Hillsboro, OR, US
- LinkedIn followers
- 500 followers
About Dipto Thakurta
20 years of leading-edge semiconductor industry experience at Intel\'s Technology Manufacturing Group. Sr. Principal engineer and group leader for test chip software design automation, shuttle program and tapeins. Hands-on technical lead. Demonstrated ability to build teams, lead, communicate, influence, collaborate and deliver with tight schedule pressures.Several years of experience in working with EDA vendor companies such as Synopsys, Mentor Graphics, etc. Co-developed and implemented several new features in EDA software working in close collaboration with vendors. Expert knowledge on Intel\'s leading-edge process technology design rules (including 5nm, 7nm, 10nm, 14nm and 22nm), DRC and DFM methodologies. Expert in DRC/ DFM rule definition, runset software coding, layout synthesis using ICV and Calibre. Developed Intel\'s first DFM scoring methodology.Expert in IC layout physical design interactions with manufacturing process/yield. Received two Intel Achievement Awards (highest award at Intel) for work in this field.
Experience
Sr Principal Engineer, Test Chip Engineering Group, Technology Design Enablement
Jan 2016 — Present · Hillsboro, OR, US
Group leader and technical lead for Test Chip Engineering Group in Design Enablement department with team members in Portland and Bangalore. Leading program management for Intel’s Multi-Product Shuttle (MPS) and all test chip design activities including test structure layout specs, reticle/die floor planning, test row allocation, design environment setup, physical design and layout automation, DRC and connectivity verification and full chip tapein. Responsible for coordination and communication meetings with various groups such as device, reliability, process integration, lithography and test hardware engineering teams.Led collaboration with EDA vendors to develop new e-test and DTCO capabilities. Responsible for reviewing contracts and providing specs for software tool development.Successfully started and led several new software enhancement and QA initiatives which helped team to deliver ~3X number of testchip tapeins compared to 2 years ago.
Education
Columbia University
Certificate of Professional Achievement
2008 — 2008
Rensselaer Polytechnic Institute
PhD, Engineering
1997 — 2001
Indian Institute of Technology, Bombay
Bachelor's degree, Engineering
1991 — 1995
Clarkson University
M.S., Engineering
1995 — 1997
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