Dipali Kanoje
IP Verification Engineer at Intel Technology India Pvt. Ltd.
- Role
- Ip Design Verification Engineer at Intel
- Location
- Pune, MH, IN
- LinkedIn followers
- 500 followers
About Dipali Kanoje
Experienced Design Verification Engineer (11 years) with a history of working on verifying RTL designs for various industries like Automobile application, Digital storage, Aviation applications. Skilled in System Verilog and UVM. Experience in VMM, UVM, Testbench and Test component development.
Experience
Ip Design Verification Engineer
Oct 2021 — Present · Pune, IN
Education
Walchand College of Engineering(A Govt. Aided Autonomous Institute),SANGLI-M.S
Engineering Diploma, Industrial Electronics
S. R. V. G. High School, Madhavnagar, Sangli, Maharashtra
S. S. C.
Walchand College of Engineering(A Govt. Aided Autonomous Institute),SANGLI-M.S
B. E. , Electronics Engineering
Skills
- Vmm
- Application-Specific Integrated Circuits (Asic)
- Modelsim
- Rtl Design
- Verification Environment Design
- Functional Verification
- Vhdl
- Verilog
- Enterprise Risk Management
- Ovm
- Unix Shell Scripting
- Perl
- Open Verification Methodology
- Systemverilog
- C
- System Verilog
- System on a Chip (Soc)
- Soc
- Fpga
- Asic
- Vlsi
- Specman
- Erm
- Perl Scripting
- Ncsim
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