Dinesh Paila
DRDO - DLRL Intern | ECE Undergrad | President @SPIE VJIT | Aspiring VLSI Engineer
- Role
- Project Intern at Dlrl
- Location
- Hyderabad, IN
- LinkedIn followers
- 500 followers
About Dinesh Paila
Driven by curiosity and a passion for technology, I’m an Electronics and Communication Engineering student focused on VLSI design. I aim to contribute to the advancements in the semiconductor industry and pursue a career that blends innovation with cutting-edge VLSI technology.
Experience
Project Intern
Apr 2025 — Present
Education
Narayana Junior College - India
Intermediate, MPC
2020 — 2022
Vidya Jyothi Institute Of Technology
BTech, Electronics and communication engineering
2022 — 2026
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