Dinesh Rangasamy

About Dinesh Rangasamy

9+ years of experience in Digital logic Front end design & Micro architecture - 2+ years of experience in CXL Transaction layer of CXL.mem & Custom accelerator to improve software performance- 3+ years experience in PCIe Design Gen5, System level & Hardware power management unit- 1+ Years of experience in TLMM & Padring design- 3+ Years experience in SoC Design Integration, Clock controller & Low power design- Experience in Silicon debugging, Interacting with firmware team, Testplan preparation- Responsible to deliver Synth/STA Constraint, CDC, UPF, CLP, PD planning, Power/timing sign-off- Implemented multiple ECO\'s including BTO/MTO ECO\'s- Experience in HLD to tape-out complete SoC cycle - Enabled silicon bringup for multiple chips - Technical leadership & leading small team to handle multiple parallel project- Experience in Modem, Mobile, Compute chip with Multi Power Domain & Multi Clock Domain high speed designProtocol : PCIe, CXL, AXI, Coherence

Experience

1. Asic Rtl Design Engineer

   Google

   Oct 2025 — Present

   TPU hardware RTL design for ML workloads

Education

• Government Higher Secondary School, Vaiyappamalai

  HSC, Maths Computer

  2007 — 2009

• P.S.G Collegee of Technology

  Master of Engineering (M.Eng.), VLSI DESIGN

  2014 — 2016

Skills

• Microsoft Excel
• Xilinx Ise
• Physics
• Embedded Systems
• Static Timing Analysis
• Digital Electronics
• Physical Design
• Rtl Design
• Linux
• Windows
• Microsoft Office
• Concept Hdl
• Cadence Encounter
• Verilog
• Python
• Cadence Virtuoso
• C
• Tanner Eda
• Research
• System Verification