Dinesh Malviya

About Dinesh Malviya

I am an IP and chip verification leader with deep expertise across advanced DDR, LPDDR, GDDR, HBM, PCIe, and CXL protocols, specializing in PHY and controller verification, methodology development, and execution excellence. With more than two decades of experience and numerous successful tape‑outs, I bring strong technical acumen combined with a proven ability to build, inspire, and enable high‑performing global teams.Currently, as a Director at AMD, I lead a high‑impact organization responsible for GDDR, HBM, and DDR PHY verification, ensuring first‑time‑right quality through robust methodologies, scalable flows, and rigorous execution. I drive strategic direction, mentor technical leaders, and champion a culture of innovation, ownership, and continuous improvement. A key focus of my leadership is advancing AI‑driven verification practices to enhance coverage, throughput, and engineering productivity.Previously, as Director of Engineering at Rambus, I led a centralized verification team supporting worldwide design groups, delivering high‑quality IP and chip products with flawless first‑pass silicon. I have extensive experience architecting verification strategies—functional, formal, mixed‑signal—and have published multiple papers at international and industry conferences.I am passionate about developing world‑class engineering organizations and continuously expanding my verification expertise to contribute to the creation of next‑generation semiconductor solutions.

Experience

1. Director Silicon Design Engineering

   AMD

   Nov 2023 — Present · Bengaluru, IN

   As a Director at AMD, I lead a high‑performing organization responsible for the verification of GDDR, HBM, and eDDR PHY solutions. My mandate is to drive technical excellence, execution rigor, and first‑time‑right quality across all stages of the verification lifecycle.In this role, I provide strategic direction, mentor technical leaders, and foster a culture of ownership, innovation, and continuous improvement. I am deeply committed to strengthening our verification methodologies, flows, and automation frameworks—continuously introducing modern best practices, scalable infrastructure, and data‑driven decision‑making. A core focus of my leadership is accelerating the adoption of AI‑driven solutions to enhance verification throughput, coverage efficiency, and engineering productivity.

Education

• SGSITS Indore (M.P.)

  BE, Electronics & Telecommunication

  1994 — 1998

• Model Higher Secondary School T.T. Nagar Bhopal

  Higher Secondary, Mathematics and Science

  1992 — 1993

Skills

• Soc
• Vlsi
• Rtl Design
• Fpga
• Systemverilog
• Functional Verification
• Pcie
• Serdes
• Verilog
• Ic
• Semiconductors
• Systemc
• Avm
• Ovm
• Uvm
• Formal Verification
• Assertion Based Verification
• Mixed Signal Verification
• Fpga Prototyping
• Memory Controllers
• Phy
• Ip Verification
• Rapidio
• Ddr and Lpddr Memory Family
• Open Verification Methodology
• Asic