Dinesh Londhe

About Dinesh Londhe

15 years of experience in Backend VLSI Design. Worked mostly on HDD, SSD Controller SoCs, Intel SKL, CNL processor SoCs.> Strong expertise in SoC full chip layout sign-off, TO & layout integration, DRC, LVS, ANT, ERC, ESD, BUMPDRC, SOC Floorplan, IP integration, IO ring planning, IO ring PG, SOC Power network, Bump planning, packaging, RDL, setting up PV flow for SOC, strong layout debug skills and worked with many internal and external vendor for integration issues.>SOC ESD-Analog IP, IO ring integration, ICV PERC ESD LUP signoff, Ansys ESD Path Finder.>Sound hands-on knowledge on Die level Power Integrity (RH-SC IR-IVD), CPM.>Block level (Synthesis, PNR, STA)> Strong expertise in physical verification. In depth experience of analyzing DRC,LVS,ERC,LVS,DFM issues, pdk ruledeck issues.>PNR (Netlist to GDS) using ICC2 (floorplanning, pns, placement, CTS, routing, physical verification, Blocks (FlASH PHY, DDR PHY, NVME, Processor blocks) contains IO PADS and lot of dependency with SOC top.> Soc top level Layout work owned for multiple SOC\'s including Bumping, RDL, IO planing, Floorplaning, PNS, Layout fixes, ESD Hard macro integration, Layout signoff (DRC, LVS ANT ESD etc). Strong debug skills to understand GDS, XOR, layout integration issues.> Expertise in doing revision eco, re-tapeout foundry checks and taping out full chip gds with all layout signoff checks in aggressive schedule.>Strong technical knowledge of ICC2, PNR and Physical verification flows and methodologies > Worked on 7nm 12nm & 28nm TSMC process nodes, Worked on 14 nm, 10 nm 10++ nm Intel process nodes.>Block and full chip Layout design expertise for microprocessor chips at Intel which includes floor-planning from scratch, Power planning, Placement, Routing, Physical verification checks, Reliability verification (SH on FINFET, EM, static and dynamic IR drop ), ECO, RCO, RC extraction.> working experience on various EDA tools for Physical Design : ICC2, ICC, SOC Encounter, PT, STAR-RC, Redhawk, ICV, Calibre, ICworkbench, Intel Internal tools.> RLS (blocks handled using ICC tool ) Layout lead and co-ordinator at Intel, worked with global teams (Israel, US, India): responsibilities includes resource planning and execution of several RLS blocks, Layout reviews.

Experience

1. R & d Ic Design Engineer

   Broadcom

   May 2024 — Present · Pune District, IN

   Full Chip Physical Verification Signoff, Tapeout Checks, ESD-LU Signoff Full Chip Integration, Bumping, RDL, IO ring, Block level PD.

Education

• Savitribai Phule Pune University

  M.Sc, Electronic Science

• Sikkim Manipal University - Distance Education

  Master of Business Administration (MBA), Project Management

• BITS Pilani Work Integrated Learning Programmes

  M.Tech Microelectronics

Skills

• Logic Synthesis
• Soc
• Physical Verification
• Physical Design
• Redhawk
• Microprocessors
• Asic
• Vlsi
• Synopsys Tools
• Cadence Encounter
• Caliber
• Icc
• Primetime
• Tcl
• Cadence Virtuoso
• Reliability