Dinesh Devaraconda
Memory Design Engineer at Intel Corporation
- Role
- Memory Design Engineer at Intel
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Dinesh Devaraconda
Familiar with EDA Tools like - RTL Compiler- Logic Synthesis - Cadence SOC Encounter –Floor Planning, Place & Route, and clock tree synthesis- Encounter Timing System –Static Timing Analysis and Crosstalk Analysis
Experience
Memory Design Engineer
Oct 2017 — Present · Bengaluru, IN
Education
Cvr College of Engineering
Bachelor of Technology (BTech), Electronics & Instrumentation Engineering
2010 — 2014
VIT UNIVERSITY
Master of Technology (MTech), VLSI Design.
2014 — 2016
Skills
- C++
- Teamwork
- Research
- Cadence Encounter
- Verilog
- Windows
- Fpga
- Asic
- Eda
- Physical Design
- Cadence Virtuoso
- Application-Specific Integrated Circuits (Asic)
- English
- Very-Large-Scale Integration (Vlsi)
- Cadence Soc Encounter
- Microsoft Office
- Vlsi
- Cadence
- Microsoft Word
- Logic Synthesis
- Static Timing Analysis
- C
- Programming
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