Dimple Mondhe

About Dimple Mondhe

Hello Brilliant Minds, I’m Dimple a R&D Engineering, Staff Engineer at Synopsys Inc. Having a proven record of successfully navigating interviews at over 7 top semiconductor companies including Intel, AMD, Samsung, Qualcomm, Cadence, Synopsys and more.‍I am a Young Professional, STEM mentor and motivational speaker from the heart. I\'d say \"Electronics is My Life, Mentoring is my Love\"I am a member of the Advanced Node Methodology Pathfinding team which is responsible for rapid (Power, Performance, Area) PPA closure on high-performance designs, using Fusion Compiler/IC Compiler II. I am working very closely with R&D and Foundry Partners, and working to isolate potential issues to help enhance the algorithms to greatly improve PPA and Runtime for the customer\'s specific designs.During the pandemic, I realized that Job Market Requirements and Young Employee’s Expectations have changed radically. In my endeavor to bridge this gap, I rediscovered my passion to mentor Young Professionals and STEM Students to succeed in Academics, Early Career Planning, and Career Progression.I am also a motivational speaker, who loves to share my knowledge and insights with young professionals and STEM students. I help them with career guidance, interview preparation, resume building, and personality development, through various platforms and channels. I believe that mentoring is my way of giving back to the community and empowering the next generation of engineers.If you want to talk more about career growth, personality development, Interview preparation & anything on mind hit me up or just email me: d••••••••@gmail.com

Experience

1. R & d Engineering, Staff Engineer

   新思科技股份有限公司

   Apr 2024 — Present · Bengaluru, IN

   I am a member of the Advanced Node Methodology Pathfinding team which is responsible for rapid (Power, Performance, Area) PPA closure on high-performance designs, using Fusion Compiler/IC Compiler II. I am working very closely with R&D and Foundry Partners, and working to isolate potential issues to help enhance the algorithms to greatly improve PPA and Runtime for the customer\'s specific designs.

Education

• University Institute of Technology, RGPV

  Bachelor's Degree, Electrical, Electronics and Communications Engineering

  2011 — 2015

• Vellore Institute of Technology

  Master of Technology - MTech, VLSI Design

  2016 — 2018

• GOVT. EXCELLENCE SCHOOL BETUL

  High School, Political Science and Government

  2008 — 2011

• AirForce school

  School

Skills

• Tcl
• Cadence Virtuoso
• Verilog Hdl
• Microsoft Office
• Xilinx Ise
• Cadence Encounter
• Perl
• Public Speaking
• Research
• Management
• Microsoft Excel
• Powerpoint
• Leadership
• Microsoft Word
• Project Management