Dilipkumar Zalavadiya

About Dilipkumar Zalavadiya

Over 18 years of experience with STA methodologies and industry-standard STA tools. Multiple foundry technology flows and methodology experience. Strong communication skills and ability to work closely with Engineering, Mask Design, and DA to integrate and converge an ASIC design.Currently Working as full-chip static timing analysis and methodology lead with following responsibilities- Develop workflow and methodology for full chip hierarchical STA timing model build- Analyze and converge on crosstalk delay, noise glitch, and electrical rules in deep-sub micron processes - Develop and support a fully automated scripts/flow to improve debug efficiency and to run full chip timing flow using Synopsys Primetime and Synopsys Flows for ASIC- Partnering with Physical Design team, highlighting issues and standard methodologies to drive signoff closure for tape out- Building/shipping test cases and working with external EDA tool vendor to facilitate STA related issues in the tool- Influence project execution and methodology while working with both external and internal tool vendors- Automate tasks to complete the design in the most efficient fashion possible- Expand and standardize design methodologies, especially those related to static timing analysis, cross-clocking domains, and multiple power domain analysis.

Experience

1. Asic Physical Design and Timing Engineer

   Tsavorite Scalable Intelligence

   Aug 2024 — Present · US

   Driving timing analysis and closure of SoCs at block level, cluster level, and full chip level.• Helped in driving backend implementation including floor-planning, clock tree synthesis, routing and timing constraints generation for timing convergence.

Education

• University of Southern California

  Master of Science (MS), Electrical Engineering (VLSI)

  2006 — 2008

Skills

• Integrated Circuit Design
• Timing Closure
• Tcl
• Spice
• Primetime
• Circuit Design
• Lvs
• Cadence
• Cadence Virtuoso
• Digital Circuit Design
• Perl
• Static Timing Analysis
• Drc
• Verilog
• Signal Integrity