Dilip Kumar
M.Tech (VLSI Design) NIT Agartala I Sr.Layout Design Engineer I Ex - Analog Devices
- Role
- Sr Layout Design Engineer at leadIC Design Pvt Ltd
- Location
- Basti, UP, IN
- LinkedIn followers
- 500 followers
About Dilip Kumar
M.tech (NITA) 2020 To 2022- VLSI Design (8.09 CGPA)*Worked on Various Projects like PSM,BGR,ESD,TX,DAC,LDO,BOOST converters, POR,Peak detectors, bias generator,Fail safe etc• Worked on various process nodes TSMC 5nm,7nm 14nm and 28 nm *Proficiency in floorpan, placement, LVS / DRC checks using calibre & Pegasus tool. • Sound knowledge of layout concepts i.e, Matching, EM & IR, ESD, Latch-up, Antenna effect, STI & WPE. • Having depth knowledge of CMOS Fundamentals, CMOS IC Fabrication flow, RC Circuit & Semiconductor Physics
Experience
Sr Layout Design Engineer
Oct 2024 — Present · Bengaluru, IN
Education
National Institute of Technology Agartala
M.tech, VLSI Design
2020 — 2022
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