Dileep Sreedharan
Verification Engineer
- Role
- Principal Design Verification Engineer at Microsoft
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Dileep Sreedharan
I am an experienced professional in Front End Verification, utilizing System Verilog/UVM…
Experience
Principal Design Verification Engineer
Sep 2023 — Present · Bengaluru, IN
Education
National Institute of Technology Calicut
B.Tech, Electronics and Communication Engineering
2005 — 2009
Sainik School Kazhakootam,Thiruvanathapuram
Higher Secondary Education, Physics,Chemistry,Bilology,Maths
1997 — 2004
Skills
- Python
- C
- C++
- Verilog
- Hardware Architecture
- Functional Verification
- Amba Ahb
- Debugging
- Perl
- Wifi
- Uvm
- Tcp/Ip Protocols
- Soc
- Systemverilog
- Ethernet
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