Dileep Kumar Saragadam

WORK HISTORY

EDUCATION

ABOUT DILEEP KUMAR SARAGADAM

My journey into VLSI began with a deep interest in how logic-level systems power real-world innovations. Since then, I’ve been driven to explore the technology behind this digital revolution—by building reusable UVM testbenches, writing synthesizable RTL, and debugging protocols across various verification projects. I’m passionate about creating functionally robust, scalable, and standards-compliant designs that contribute to first-time-right silicon. Core Technical Skills Verilog, SystemVerilog, and UVM methodology RTL coding and testbench development Functional Coverage & Code Coverage Constraint Random Testing and Assertions Protocols: AXI3 Verification Planning and DebuggingKey Projects AXI3 VIP development with layered sequences and UVM-based verification Dual Port RAM (SoC-level) design and functional verification Router 1x3 design and UVM-based verification with corner case analysis Mod-12 Up/Down Counter with 100% Functional Coverage using SystemVerilog