Dijeesh K
Validation engineer |Texas Instruments
- Role
- Post Silicon Validation Engineer at Texas Instruments
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Post Silicon Validation Engineer
Jul 2019 — Present · Bangalore, IN
Education
ST. Joesph's B.H.S.S
10+2
2007 — 2009
Govt. Engineering College Kozhikode
Bachelor of Technology (BTech)
2010 — 2014
NIELIT CALICUT
Master of Technology - MTech
2017 — 2019
Prolific System and Technologies
PG diploma in industrial automation
2014 — 2015
Skills
- Envigil Scada
- C
- Scada
- Analytical Instruments
- Plc Allen Bradley
- Wonderware Scada
- Python
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