Dhruv Saxena

About Dhruv Saxena

In an Infinite Loop of Seeking Knowledge **•Programming Languages: SystemVerilog, Verilog, UVM, C, Assembly, Python, Linux shell scripting basics •Verification: SV, UVM, Assertions, Coverage, Constrained randomization•Design: Computer architecture, Static Timing Analysis, CDC, Physical design, Signal Integrity basics•Memory & Interfaces: DDR3, AMBA protocols (AHB, APB, AXI4-Lite)•EDA Tools: VCS, Design Compiler, OpenTimer, GCC

Experience

1. Senior Design Verification Engineer

   Samsung Semiconductor

   Feb 2023 — Present

Education

• San José State University

  Master of Science (M.S.), Electrical and Electronics Engineering

  2015 — 2016

• Maharshi Dayanand University

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2006 — 2010

Skills

• Microsoft Office
• Vlsi
• Computer Architecture
• Rtl Coding
• Universal Verification Methodology (Uvm)
• Field-Programmable Gate Arrays (Fpga)
• Cadence Virtuoso
• Linux
• Functional Verification
• Organizational Leadership
• Functional Coverage
• Python
• Amba Ahb
• Microsoft Excel
• C++
• Microsoft Word
• Verilog
• Systemverilog
• Microsoft Powerpoint
• Assertion Based Verification
• Application-Specific Integrated Circuits (Asic)
• Teamwork
• Team Management
• Nc-Verilog
• Problem Solving
• Very-Large-Scale Integration (Vlsi)
• Vhdl
• Code Coverage
• Communication
• Analysis
• Rtl Verification
• Cmos
• C
• Programming
• Static Timing Analysis
• Synopsys Tools
• Management
• Leadership
• Soc
• Rtl Design