Dhruv Gor
Design Verification Engineer @ INTEL | M.Tech ’26 VLSI Design @Nirma University | VLSI Enthusiast |
- Role
- Design Verification Engineer at Intel
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Dhruv Gor
Working as a Mixed Signal Design Verification Engineer at Intel working as a part of DDR5 IP Verification Team, currently pursuing M.Tech in VLSI Design from Nirma University, Ahmedabad. What I Do • Contribute to DDR5 IP verification, focusing on Debugging and verification activities. • Implement verification flows that improve compile time and development efficiency • Develop SystemVerilog checkers and testcases to validate RTL behavior • Handle regressions and failure analysis, reducing manual debugging effort • Verify register behavior (read/write, read-only, write-only) to ensure correct access control Technical Skills • Languages: Verilog, SystemVerilog, basic UVM, Python scripting • Verification: Functional verification, testbench development, regression analysis • Tools: Synopsys VCS, Verdi, Venus (Regression), QuestaSim, Xilinx Vivado • Worked on Design and Verification of APB Protocol, RAM, FIFO using Xilinx and QuestaSim tools.
Experience
Design Verification Engineer
Apr 2026 — Present · Bengaluru, IN
Education
Shree Swaminarayan Public School - India
H.S.C, Science Stream
Army Public School (APS) Bhuj
10th
Birla Vishvakarma Mahavidyalaya
Bachelor of Technology - BTech, Electronics Engineering
Nirma University
M.Tech, VLSI Design
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