Dhruva Pandey
Design Verification Engineer at AMD
- Role
- Design Verification Engineer at AMD
- Location
- Hyderabad, TG, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Design Verification Engineer
Feb 2022 — Present
Education
Shri Shankaracharya College of Engineering and Technology
Bachelor of Engineering, Electronics and Communication in Engineering
2005 — 2009
Indian Institute of Technology, Kanpur
M.tech., Microelectronics Vlsi & Display Technology
2009 — 2011
Skills
- Application-Specific Integrated Circuits (Asic)
- Vlsi
- Circuit Design
- Windows
- Perl
- C
- Cadence Virtuoso
- Asic
- Scripting
- Vhdl
- Systemverilog
- Unix
- Computer Architecture
- Very-Large-Scale Integration (Vlsi)
- Linux
- Modelsim
- Verilog
- Debugging
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