Jay Dholakia

About Jay Dholakia

Accomplished Design engineer with over eight years of industry experience in logic design of high performance PCIe/CXL processor cores and expertise in ASIC and FPGA Design. Proficient in all phases of SOC Design, synthesis, timing analysis, verification, CDC, linting, as well as post-silicon validation, I am dedicated to pioneering innovative solutions that enhance the performance and capabilities of digital systems.Skill set:• VLSI: Microarchitecture, CDC, Lint, Timing closure, synthesis, PPA, Low power design, ECO• Programming Languages: Verilog, System Verilog, UVM, C/System C, Python, VHDL, C++• Software: NC Sim, Cadence Virtuoso, Verdi, ModelSim, Synopsys VCS, Quartus II

Experience

1. Silicon Design Engineer

   AMD

   Oct 2025 — Present · Austin, TX, US

Education

• Northwestern University

  Master of Science (MS), Electrical and Electronics Engineering

  2013 — 2014

• Manipal Institute of Technology

  Bachelor of Engineering (BEng), Electrical, Electronics and Communications Engineering

  2009 — 2013

Skills

• Automation
• Logic Synthesis
• Physical Design
• Cadence Virtuoso
• Microsoft Office
• Vlsi
• Microcontrollers
• Cmos
• System Verification
• Lvs
• Cadence
• Ic
• Fpga
• Asic
• Visual Basic
• C
• Programming
• Pcie
• Verilog
• Rtl Design
• Semiconductors
• Llt Scripting
• Nand Flash
• Integrated Circuit Design
• Espresso
• C++
• Computer Architecture
• Rtl Coding
• Python
• Modelsim
• Debugging
• Perl
• Embedded Systems
• Eda
• Quartus
• Xilinx Ise
• Electronics
• Spice
• Drc
• System Verilog