Dhirendra Manohar Rahul
Principal Engineer DFT
- Role
- Principal Engineer Dft at Intel
- Location
- Allentown, PA, US
- LinkedIn followers
- 500 followers
Experience
Principal Engineer Dft
Jul 2025 — Present · Boxborough, MA, US
Education
Cochin University of Science and Technology
Bachelor of Technology (B.Tech.), Electrical, Electronics and Communications Engineering
2001 — 2005
Skills
- Vhdl
- Processors
- Vlsi
- Primetime
- Static Timing Analysis
- Dft
- Semiconductors
- Modelsim
- Application-Specific Integrated Circuits (Asic)
- Soc
- Perl
- Eda
- Timing Closure
- Jtag
- Hardware Architecture
- C
- Debugging
- Usb
- Tcl
- Atpg
- Arm
- Rtl Design
- Very-Large-Scale Integration (Vlsi)
- Asic
- Bist
- Verilog
- Rtl Coding
- System on a Chip (Soc)
- Logic Synthesis
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