Dheeraj Verma
Senior R&D Engineer @ Synopsys Inc | Design Flow Logic Synthesis | Standard Cell Libraries | M.Tech in VLSI | Digital Electronics | Verilog | STA | CMOS | ASIC & Physical Design Flow
- Role
- Senior R & d Engineer at 新思科技股份有限公司
- Location
- Surat, GJ, IN
- LinkedIn followers
- 500 followers
About Dheeraj Verma
Working as Design Flow Logic Synthesis Engineer specialized in standard‑cell library…
Experience
Senior R & d Engineer
Feb 2024 — Present · Bengaluru, IN
Education
Sardar Vallabhbhai National Institute of Technology, Surat
M.Tech
2020 — 2022
Institute of Engineering and Technology
B.Tech
2016 — 2020
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