Dhaval Patel
Silicon Validation Engineer
- Role
- Senior Silicon Validation Engineer at Google
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
Experience
Senior Silicon Validation Engineer
Apr 2025 — Present · IN
Education
Chandubhai S. Patel Institute of Technology
BE - Bachelor of Engineering, VLSI design
2008 — 2012
Axay Highschool
HSC, science
2006 — 2008
Skills
- Orcad
- Microcontrollers
- Altera Quartus
- C
- Xilinx Ise Navigator
- Version Control Doors
- Ni Labview
- Embedded Systems
- Actel Libero Ide
- Satellite Systems Engineering
- Automotive Electronics
- Pspice
- Vhdl
- Electronics
- Fpga
- Rtl Design
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