Dhaval Girishkumar Shah

Principal SoC/RTL Design Engineer | Verilog, AXI IP, ASIC, TCP/IP |NPU Data movement | IP Engineer

Role
Principal Design Engineer at Cadence
Location
Pune District, MH, IN
LinkedIn followers
500 followers

About Dhaval Girishkumar Shah

Completed B. Tech. in 2012 (WCE, Sangli) and M.Tech (IIT B, 2014). Joined the corporate immediately. Good hands on Design Engineer in the field of FPGA/ASIC • Good hands on Experience in System Verilog, Verilog • Hands on Linting, CDC, using power optimized techniques, and STA optimization • Encoding spikes related to Neuromorphic computing • Implemented AXI 4 master/slave read, write engines. Knowledge of protocols like AXI, AXI lite, I2C, SPI protocols • Good Knowledge of ASIC life cycles, FPGA, & SoC Design & Verification Life Cycles. • Good Knowledge in both functional and gate level simulations • Well versed in setting up software top and hardware top in a Top Level Emulation test bench • Excellent debugging skills • Good Documentation skills • Familiar with concepts of C, C++ and Object Oriented Methodology. • Have good communication skills, interpersonal relations, analytical skills, hardworking and result oriented as an individual and in a team. • Willing to learn new skills and ability to learn fast. • Technical support to team members • 10+ year of relevant experience • Excellent academic record. Specialties: SystemVerilog,Verilog,UVM,FPGA,AXI4, Xilinx ISE suite 11,Model Sim 10,Questa Sim 12c System Verilog UVM/OVM/VMM based SoC / ASIC/ IP Design Verification on assertion based Constrained Random Verification (CRV) with Functional and Code coverage and RTL (Verilog HDL & VHDL) development. DM me to connect

Experience

  1. Principal Design Engineer

    Cadence

    Jun 2022 — Present · IN

    Implementing AXI4 Protocol for the IP group for communicating to external systems. Understanding the IP. Understanding the AXI protocol, and implementing the requirements in verilog. Upbringing and debugging. Synth and Lint support. AXI Master and AXI Slave side implemented.

Education

  • Sangli High School

    High School, Computer Science

    2006 — 2008

  • Indian Institute of Technology, Bombay

    Master's Degree, Biomedical/Medical Engineering (Signal Processing using wavelets having application in Biomedical)

    2012 — 2014

  • Walchand college of Engg

    Bachelor of Technology (BTech), Electrical, Electronics and Communications Engineering

    2008 — 2012

  • Emmanuel English School, Sangli

    SSC, Basic School

    1997 — 2006

Skills

  • Wavelets
  • Grinder
  • Verilog
  • Powerpoint
  • Microsoft Excel
  • Jmeter
  • Performance Testing
  • Signal Processing
  • Fpga
  • Java
  • System Verilog
  • Core Java
  • Testing
  • Data Structures
  • Bhagvat Gita
  • Research
  • Algorithms
  • Matlab
  • C
  • Programming
  • Html
  • Biomedical Engineering
  • Sql
  • Linux
  • Microsoft Office
  • C++
  • Embedded Systems
  • Microcontrollers
  • Digital Circuit Design
  • Engineering Mathematics
  • Mysql
  • Electronic Circuit Design
  • J2ee Web Services
  • Electronics

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Dhaval Girishkumar Shah — Principal Design Engineer at Cadence in Pune District, MH, IN | Unifers