Dharshini S
Aspiring VLSI Engineer | RTL Design | Functional Verification (SystemVerilog, UVM) | Physical Design | Synopsys (VCS, Verdi, Design Compiler, ICC2)
- Role
- Associate Content Editor at The Institution Of Electronics And Telecommunication Engineers Iete
- Location
- Chennai, TN, IN
- LinkedIn followers
- 500 followers
About Dharshini S
I’m Dharshini S, a pre-final year Electronics and Communication Engineering student at Easwari Engineering College, Ramapuram, with a strong interest in VLSI design and embedded systems.My primary focus lies in RTL design, functional verification, and physical design. I have hands-on experience with SystemVerilog and UVM, where I built verification environments from scratch as part of a real-time project. I have also worked with Synopsys tools such as VCS and Verdi for simulation and debugging, and gained exposure to Design Compiler and ICC2 as part of my learning in physical design.Alongside VLSI, I have worked on embedded systems projects involving ESP32, IoT-based monitoring, and motor control, which helped me understand real-time system design and hardware-software integration.I enjoy solving technical problems and continuously exploring tools and technologies that bridge theory with practical implementation. I am a quick learner, detail-oriented, and committed to building efficient and reliable engineering solutions.I’m currently looking to grow further in the semiconductor domain and contribute to real-world VLSI design and verification challenges
Experience
Associate Content Editor
The Institution Of Electronics And Telecommunication Engineers Iete
Sep 2025 — Present · Chennai, IN
Education
Easwari Engineering College(SRM Group)
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
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