Dharshine R S
Project Engineer at CDAC | Design Verification Engineer | UVM & SystemVerilog | IP & SoC Verification
- Role
- Project Engineer at Cdac - Thiruvananthapuram
- Location
- Thiruvananthapuram, KL, IN
- LinkedIn followers
- 500 followers
About Dharshine R S
I am a Design Verification Engineer with 2.5+ years of hands-on experience in functional verification of IP and system-level designs using SystemVerilog and UVM. Currently working as a Project Engineer at CDAC, where I continue to contribute to high-impact engineering projects in advanced technology domains.My professional journey includes verifying complex systems such as night vision camera solutions and Ethernet switch designs, along with the development and verification of reusable Verification IPs. I have strong expertise in building robust testbenches, creating verification environments, debugging complex issues, and ensuring design quality from block to system level.I am passionate about delivering reliable silicon, learning emerging technologies, and continuously improving verification methodologies. I thrive in collaborative environments and enjoy solving challenging engineering problems. Core Skills:• SystemVerilog, UVM• IP & SoC Functional Verification• Testbench Development & Debugging• Protocol & System-Level VerificationI’m always open to connecting with professionals in VLSI, semiconductor, and embedded systems domains.
Experience
Project Engineer
Feb 2026 — Present · Thiruvananthapuram, IN
Education
Arunachala College of Engineering for Women
Bachelor of Engineering - BE, Electronics and Communication Engineering
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