Dharshan V
Masked Design Analog | Engineering Research & Development
- Role
- Associate at Capgemini Engineering
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Dharshan V
Analog Layout Design Engineer with hands-on experience in advanced semiconductor…
Experience
Associate
Apr 2024 — Present · Bengaluru, IN
Analog Layout Design Engineer | R&D Team+ Collaborating on an experimental analog layout project with Intel using 5nm technology.+ Reviewing and validating client-generated auto-layouts, ensuring compliance with design rules and providing critical feedback for tool improvements.+ Designing functional analog layouts for leaf and intermediate cells from scratch, using matching techniques like common centroid and interdigitization.+ Ensuring all layouts are DRC and LVS clean, using Cadence Virtuoso for full custom layout and verification.
Education
New Horizon College of Engineering
Bachelor of Engineering - BE, Electrical, Electronics and Communications Engineering
2019 — 2023
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.