Dharmesh Gurjar

About Dharmesh Gurjar

I have 3.5+ years of experience in the Design and verification Domain. Currently working on UCIe controller IP and subsystem Verification. Also I have worked on PCIe(PHY layer verification) and CXL2.0(LInk Layer and ARB/MUX Layer verification) with the demostrated history of working with different industry standard tools and technology. I am highly Self Motivated and commited entry level engineer who is eager to learn new things, Having Good analytical and Communication Skill.Skills-1) HVL Language - Verilog and SystemVerilog2) Verification Methodology - UVM3) Constraints Random Verification4) System Verilog Coverage(SVG)5) System Verilog Assertion(SVA)5) Shell/Perl ScriptingExperience in industry Protocol.1) UCIe2)AHB2APB Bridge3)AHB4)AXI (Specification understanding)5)PCIe 5.0(PHY Layer verification)6)CXL 2.0(Link Layer and ARB/MUX Layer verification)Interests are Digital Electronics & Computer Hardware, ASIC Design and Functional Verification, Scripting.

Experience

1. Senior Design Verification Engineer

   Qualcomm

   Dec 2024 — Present · Bengaluru, IN

Education

• P. P. SAVANI VIDHYA SANKUL

  Higher Secondary

  2014 — 2016

• The Maharaja Sayajirao University of Baroda

  BE - Bachelor of Engineering, Electronics engineering

  2016 — 2020