Dharmendra Yadav
Intern @ NXP || M.Tech in VLSI DESIGN-25 || NIT Delhi
- Role
- Intern at 恩智浦半导体
- Location
- Gorakhpur, IN
- LinkedIn followers
- 500 followers
About Dharmendra Yadav
NXP Semiconductors has provided hands-on exposure to PDK,Physical design, Verilog, and Python, enabling contributions to digital IC design workflows. This role supports the development of technical skills aligned with the semiconductor industry\'s needs. Currently pursuing an MTech in VLSI at NIT Delhi, with a focus on low-power VLSI design and STA. Academic and professional experiences reflect a commitment to advancing expertise in VLSI, driven by a passion for semiconductor innovation and technology.
Experience
Intern
Jul 2024 — Present · Noida, IN
Developed and validated Process Design Kits (PDKs) using Cadence Virtuoso, enhancing design efficiency. • Implemented shell scripting to automate testing processes, reducing manual effort by 30%. • Conducted aging simulations and FGR tests, ensuring reliability and performance of semiconductor products.
Education
National Institute of Technology Delhi
Master of Technology - MTech
GALGOTIA S COLLEGE OF ENGINEERING AND TECHNOLOGY, GREATER NOIDA
Bachelor of Technology - BTech
Find verified contacts for anyone on LinkedIn
Unifers gives sales teams verified emails and direct dials, enriched profiles, and outreach that lands in the inbox.
Free plan included · No credit card required
This profile is compiled from publicly available professional sources. Unifers is not affiliated with or endorsed by LinkedIn. Request removal of this profile.