Dharani Patil
GPU Platform Hardware Design Engineer @ Intel | Application Engineer Intern at Ansys | MS EE Graduate at SJSU | Sr.CAD Engineer | ASIC Digital Design Engineer
- Role
- Gpu Platform Hardware Design Engineer at Intel
- Location
- Santa Clara, CA, US
- LinkedIn followers
- 500 followers
About Dharani Patil
With over Six years of experience in ASIC design and CAD engineering, I am passionate about developing innovative solutions for power estimation and optimization in the semiconductor industry.As GPU hardware engineer at Intel, I’m currently contributing to the Low Power Graphics - Power Attainment Team. My work primarily centers around optimizing workloads associated with GPUs, aligning with the Graphics design team\'s objectives. I have hands-on experience in low power design, Synthesis, Logic Equivalence Check, Power analysis /Estimation and ECO flow.I am eager to apply them to new challenges and opportunities.
Experience
Gpu Platform Hardware Design Engineer
Feb 2024 — Present · US
Education
San José State University
Masters , Electrical and Electronics Engineering
Dr. Ambedkar Institute Of Technology
Bachelor of Engineering (BE), Electrical, Electronics and Communications Engineering
2010 — 2014
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