Dhanya Hegde

About Dhanya Hegde

Experienced Verification Engineer in the semiconductors industry with expertise in System Verilog, UVM, RTL Coding, Developing Sub-System Testbench, functional coverage closure- I am also currently associated with MUST Research Club, we work in the field of cognitive computing, data science and advanced analytics. We organize lectures, seminars and workshops across India.(Website - on Experience : Verilog, System Verilog and UVM based verification environment for IP/subsystem/NoC/SoC verification using all ARM-AMBA protocols (AXI, AHB,APB, ACE,CHI & DTI,LTI,LPI) & sub-system RTL Design verification.

Experience

1. Manager Silicon Design Engineering

   AMD

   Jan 2026 — Present · Bengaluru, IN

Education

• Manipal Institute of Technology

  Master's degree, VLSI Design & Verification

  2014 — 2016

• Visvesvaraya Technological University

  Bachelor of Engineering (B.E.), Electrical, Electronics and Communications Engineering

  2009 — 2013

• Kendriya Vidyalaya Indian Institute of Science

  High School, Electronics

  1997 — 2009

• Indian Institute of Science (IISc)

  Centre for Nano Science & Technology (CeNSE)

  2015 — 2016

Skills

• Windows
• Tcl
• Functional Verification
• Power Electronics
• Microsoft Excel
• Fpga Prototyping
• Matlab & Simulink Modelling
• Static Timing Analysis
• Digital Electronics
• Cadence Virtuoso Layout Editor
• Rtl Design
• Embedded C
• Microsoft Office
• Vlsi
• Microsoft Word
• Python
• Assertion Based Verification
• Fpga
• Integrated Circuit Design
• Microprocessors
• Ni Labview
• C
• Programming
• Asic
• System Verilog
• Vivado & Sdk
• Debugging
• Soc
• Xilinx Ise
• Xilinx
• Matlab
• Very-Large-Scale Integration (Vlsi)
• Vhdl
• Simulations
• Code Coverage
• Cadence Encounter
• Uvm
• Microcontrollers
• Perl
• Embedded Systems