Devesh K.
Senior Silicon Design Engineer in CPU group at AMD
- Role
- Senior Silicon Design Engineer at AMD
- Location
- North Brunswick, NJ, US
- LinkedIn followers
- 500 followers
About Devesh K.
An Aspiring Engineer with a passion for VLSI systems.Former Power Grid intern in CAD methodology group at Samsung Austin Research CenterCurrently, Graduate Research Assistant at Georgia Institute of Technology GPA : 4.0/4.0Software Skills: C++, MATLAB, Arduino, Python, MPI, CUDAVLSI softwares : Cadence Virtuoso, Cadence Innovus, Garnet2.0, Redhawk, Redhawk_sc, ICC2, SEMulator3D, silicon smart Relevant Graduate Courses completed :1. Advanced Very-Large-Scale-Integration 2. Advanced Computer Architecture 3. Physical Design Automation4. Interconnection Networks 5. Digital System Test6. Advanced Programming Techniques7. Quantum Computing8. Gigascale Integration9. Biomedical Applications of MEMS10. Special Problem : FINFET library using ASAP7 PDK
Experience
Senior Silicon Design Engineer
May 2023 — Present · Boston, MA, US
Contributing to the Physical Design of advanced CPU core architectures using cutting-edge technologies; successfully completed multiple tapeouts as partition owner- Collaborating closely with EMIR, Gate Level Simulations and Scan/ATPG teams to enhance product quality and design robustness- Specializing in tile maintenance and timing analysis to support the development of high-quality, reliable silicon- Acting as a liaison between the Physical Design team and multiple analysis teams to align on deliverables, set clear expectations, and coordinate cross-functional issue resolution through effective bug tracking and fix management
Education
Georgia Institute of Technology
Master of Science - MS, Electrical and Computer Engineering
2018 — 2020
Sardar Patel College of Engineering (SPCE),Mumbai
Bachelor of Technology, Electrical Engineering
2014 — 2018
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