Devendra Dev Kumar Maurya
Technical Lead DFT STM || SDE-2 AMD || M.Tech-VLSI-IIITDelhi || B.Tech-ECE-K.I.E.T
- Role
- Technical Lead (Dft) at 意法半導體
- Location
- Lucknow, UP, IN
- LinkedIn followers
- 500 followers
About Devendra Dev Kumar Maurya
Worked as a DFT Engineer at AMD. My role was to perform Scan Insertion, Resolve DRC violation related to Scan Insertion and ATPG at the Core Level.Performing pattern generation for Intest & Extest mode(Stuck-at & Tdf) at the Core Level. Perform Coverage analysis for both Stuck-at & Tdf mode. Target was to achieve 99% test coverage for stuck-at, while greater than 95% for Tdf. Later simulating generated Chain & Capture pattern and debugging failing patterns and finding the root cause of the failure and fixing them. I also have an understanding of SOC level concepts. Good Understanding of Good knowledge DFT related concepts which include SpyGlass Checks, EDT concepts, Lock-Up Latch, Wrapper concept, Clock-Gating Cells, Test-Point Insertion, OCC Concepts, Faults Types, Fault Modelling, ATPG Algorithm.DFT Related Tools- Design Compiler, Fusion Compiler, Tessent TestKompress, Verdi & VCS.
Experience
Technical Lead (Dft)
Apr 2025 — Present · Noida, IN
Working as a DFT Engineer on STM32 Microcontroller Products.
Education
Indraprastha Institute of Information Technology, Delhi
Master's degree, VLSI
2019 — 2021
KRISHNA INSTITUTE OF ENGINEERING AND TECHNOLOGY, GHAZIABAD
Bachelor of Technology - BTech, Electronic and Communications Engineering
2014 — 2018
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