Devendra Gour
Senior Engineer || Digicomm Semiconductor Pvt Ltd || Qualcomm Client || Bengaluru || Noida
- Role
- Engineer Ii at Qualcomm
- Location
- Bhopal, MP, IN
- LinkedIn followers
- 500 followers
About Devendra Gour
Into VLSI domain ( Physical Design, Synthesis and STA)I am a Senior Physical Design Engineer with 3+ years of hands-on experience in ASIC Physical Design, currently contributing to advanced Qualcomm projects. My expertise allows me to work across cutting-edge technology nodes including 2nm, 3nm, 4nm, and 45nm, with multiple tape-outs successfully completed and others in progress.I have strong experience across the complete physical design flow using Cadence Innovus, including floorplanning, placement, CTS, routing, timing closure, RC extraction, ECO implementation, and sign-off. I have worked extensively on low-power, congestion-prone, and multi–power domain designs, addressing complex challenges related to DRC, DRV, Crosstalk, SI, EM, IR, and antenna violations.I am always open to learning, collaborating, and taking on challenging opportunities in advanced ASIC Physical Design.
Experience
Engineer Ii
Dec 2025 — Present · Noida, IN
Education
Sagar Group of Institutions - SISTec
Bachelor of Technology - B.Tech
2018 — 2022
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