Dev Desai
- Role
- Hardware Engineer 2 at Microsoft
- Location
- Seattle, WA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Dev Desai
As an Senior FPGA Design Engineer in the Microsoft Azure Networking team for the past six…
Experience
Hardware Engineer 2
Aug 2020 — Present
Skills
- Semiconductor Device
- Management
- C++
- C
- Image Processing
- Verilog
- Ethernet Sw
- Powerpoint
- Vhdl
- Microsoft Powerpoint
- Perl
- Hdlc
- Rtl Verification
- Very-Large-Scale Integration (Vlsi)
- Programming
- Modelsim
- Design Verification Testing
- Microsoft Excel
- Field-Programmable Gate Arrays (Fpga)
- Html
- Static Timing Analysis
- Logic Synthesis
- Rtl Coding
- System Verilog
- Place & Route
- Computer Architecture
- Nios Ii
- Microsoft Azure
- Research
- Matlab
- Microsoft Office
- Digital Signal Processing
- Systemverilog
- Python
- Synopsys Tools
- Altera Quartus
- Universal Verification Methodology (Uvm)
- Cadence Virtuoso
- Cisco Routers
- Microsoft Word
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