Devavrat Sabnis
Senior Design Verification Engineer @ Intuitive
- Role
- Senior Design Verification Engineer at Intuitive
- Location
- San Jose, CA, US
- LinkedIn followers
- 500 followers
About Devavrat Sabnis
I am a self-motivated Design Verification Engineer with over 10 years of experience in the full verification cycle, specializing in both Functional and Fundamentals of Verification. I have strong expertise in scripting with Python for regression testing and extensive experience with TLMs, Directed Tests, and Constrained Random Testing using SystemVerilog, OVM, and UVM. Additionally, I am skilled in SystemVerilog Assertions (SVA), Code Coverage, and Functional Coverage. I have hands-on experience with major ASIC tools such as VCS, DVE, Verdi, Xcelium, Incisive, Simvision, and Questasim, as well as Xilinx Vivado and Altera Quartus in both Linux and Windows environments.
Experience
Senior Design Verification Engineer
Aug 2025 — Present · Sunnyvale, CA, US
Education
Savitribai Phule Pune University
Bachelor of Engineering - BE, Electronics & Telecommunication
2006 — 2010
New York University
Master of Science - MS, Electrical Engineering
2011 — 2013
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