Devansh Rajoria

About Devansh Rajoria

Hi, I have 6+ year of experience in Memory Circuit Design.FINFET - TSMC N3E/N3P/N6EFDSOI - Samsung 18/28 nm Bulk - TSMC 22nm, Samsung 40nm-SKILL SETS - Complete understanding of SRAM circuit specially Ultra Low Leakage(ULL). Setup/Hold timings, Cycle time, Functional margins validations and qualifications. Self-time tuning (Read & Write margin) and Access Disturb Margin (ADM). Bitcell Analysis, Sense Analysis, Latch Analysis, Xtalk and Glitch analysis, CPTS (Tight Stimuli) Memory characterization (Timing, Power, Leakage, PinCap, DeCap) RC extraction and leafcell plugin. Tiler coding of compiler (includes adding new tiles, enabling features such as SCAN, BIST and Power Gating). Worked on NanoTime for timing and coupling analysis, Voltus-Fi XL for EMIR. Proficient in C/C++, Perl and Shell scripting. Physical Verifications (DRC, LVS, Antenna Check, Latchup, EM & IR). Some experience in RTL design using Verilog HDL.

Experience

1. Senior Design Engineer

   Arm

   Apr 2025 — Present · Bengaluru, IN

Education

• Guru Gobind Singh Indraprastha University

  Bachelor of Technology, Electrical, Electronics and Communications Engineering

  2015 — 2019