Dejan Vulevic
Design Verification Manager at Meta
- Role
- Design Verification Manager at Meta
- Location
- San Francisco, CA, US
- LinkedIn followers
- 500 followers
EngineeringView LinkedIn profile
About Dejan Vulevic
ASIC verification, pre/post silicon validation, architecture and design of complex SoCs, team/org build up and development. From individual contributor to senior leadership skills.
Experience
Design Verification Manager
Feb 2019 — Present · San Francisco, CA, US
Education
University of Belgrade
Master of Science - MS, Electrical Engineering/Computer Science
Skills
- Uvm_Reg
- C
- Digital Signal Processors
- Ovm
- Modelsim
- Functional Verification
- Team Leadership
- Hw/Sw Integration
- Performance Testing
- Vhdl
- C++
- Tcl
- Specman
- Open Verification Methodology
- Verilog
- Processors
- Cadence Imc
- Perl
- Systemverilog
- Cadence
- Clearcase
- Rtl Design
- Uvm
- System on a Chip (Soc)
- Mipi
- Soc
- Integrated Circuit Design
- Ncsim
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