Deep Kalola

About Deep Kalola

8 years of related experience in semiconductor back-end domain with 8+ tape-outs; gaining experience on complete ASIC flow development by reducing TTM through chip deadlines and optimizing PPA’s through various utilities.Hands-on experience with various technology nodes; 28nm HPM, 16nmFF+GL, 7nmFPP, 5LPE.Have excellent credibility for sign-off, timing complexities, and physical verification closure.Have depth understanding on low power checks, deployments, and pre-closure to mitigate major issues in the design cycle. Mitigating project cycle through team management, methodology enhancement, and DA.Expert in developing in-house utilities/flows with documentation; to fix, validate and reduce TAT of sign-off checks (incl. Antenna/IR/SIGEM/DRC/LVS violations on clock network as well as signal network on each hierarchy of design).

Experience

1. Senior Staff Engineer

   Samsung Electronics

   Mar 2021 — Present

Education

• Sainik School Balachadi

  Higher Secondary

  2002 — 2008

• Gujarat Technological University

  Bachelor's degree, Electrical, Electronics and Communications Engineering

  2009 — 2013

Skills

• Static Timing Analysis
• Digital Electronics
• C
• Vlsi
• Application-Specific Integrated Circuits (Asic)
• Asic
• Verilog
• Microcontrollers
• Physical Design
• Cmos
• Simulations
• Embedded C
• C++