Deepesh Chaturvedi

About Deepesh Chaturvedi

Experience Summary Verification of various standard communication and interconnect protocols.2. Verification Strategy, Test Plan and Test Bench development using the standard process and methodologies. Test Bench Setup, Test Execution and Debugging of IPs and SoCs.3. Integration and Usage of standard VIPs.4. Knowledge of System Verilog, UVM, Verilog and C (Basic) languages.6. Developed mixed language test environments having SV, C and E-languages. Implementation and usage DPIs.7. Developed auto checkers based on SV Assertions.8. Functional Coverage plan development. FC implementation and analysis.9. Code Coverage configuration, analysis and implementation.10. ROM Code debugging and implementation for ARM Cortex processor.11. SVN and Design Sync repository configuration and maintenance. SVN and Apache installation and configuration.12. Scripting for automation and verification environment and other basic SUNBURST DESIGN - SYSTEM VERILOG OVM/UVM VERIFICATION TRAINING - by Clifford E. Cummings Skills Tools :HVL Tools : Cadence NC Sim (mostly used), Model Sim, VCS Waveform viewer : Simvision (mostly used), Debussy, DVEHDL Languages : System Verilog, Verilog, e- languageMethodology : UVM, OVM, e-RVMScript Languages : Perl, Bash, C-shellConfiguration : SVN, Design Sync and CVS.Bus protocols : AXI, AHB, SATA (recently). PCIe, I2C, MDIO, OCP (earlier)My career goal is to acquire technical skills to be an Architect for System Designs or Verification.

Experience

1. Engineer, Sr Staff - Ic Design

   Broadcom

   Jun 2014 — Present · Bangalore, IN

   Verification of IP Blocks

Education

• Motilal Nehru National Institute Of Technology

  B.Tech, Electronics and Communication

  2002 — 2006

• Subhash Smarak Inter College

  Intermediate, PCM

  1994 — 2000

Skills

• Semiconductors
• Verilog
• Soc
• Vhdl
• Perl
• I2c
• Open Verification Methodology
• Vlsi
• Functional Verification
• Asic
• Uvm
• Pcie
• Amba Ahb
• Systemverilog
• Debugging