Deepesh Anjankar

About Deepesh Anjankar

Area of interest: Physical design.Currently working physical design engineer at Samsung. Working from RTL to GDS including synthesis, PNR, physical verification, timing closure, constraints cleanup, FM and VSLP check. Previously worked as Application engineer at Synopsys and also worked as Physical Design Engineer at INTEL.Completed M.Tech in 2016 in VLSI Design from Visvesvaraya national institute of technology, Nagpur, Maharashtra.I have good knowledge in back end digital VLSI Design right from RTL synthesis to GDS which includes RTL synthesis, block/Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, EM analysis, Physical Verification, logical Equivalence checking.>EDA Tools - Cadence- GENUS, RTL Compiler, Conformal LEC, INNOVUS, SoC Encounter, Virtuoso, ETS, EPS, VOLTUS, TEMPUS.> Synopsys- Design Compiler, Fusion compiler, ICC, ICC2, Star RC, prime time, Formality, RTL-Architect.>Hardware Description Languages : VHDL, Verilog.>Scripting Languages : Perl, Tcl >Design Tool : ModelSim>FPGA Synthesis Tools : Xilinx ISE

Experience

1. Physical Design Engineer

   Samsung Semiconductor

   Dec 2021 — Present · Bengaluru, IN

Education

• Modern School

  HSC, CBSE, Physics,Chemistry,Maths

  2008 — 2009

• Visvesvaraya National Institute of Technology

  Master of Technology (M.Tech.), VLSI Design

  2014 — 2016

• Nagpur University

  Bachelor of Engineering (B.E.), Electronics Engineering

  2009 — 2013

• Modern School

  SSC, CBSE, Science

  2006 — 2007

Skills

• Rtl Design
• Raspberry Pi
• Cmos
• Xilinx
• Rf Design
• Asic
• Layout Versus Schematic (Lvs)
• Genus
• Verilog
• Comsol
• Xilinx Ise
• C
• Rtl Compiler
• Integrated Circuit Design
• Application-Specific Integrated Circuits (Asic)
• Research
• C++
• Design Rule Checking (Drc)
• Matlab
• Spice
• Innovus
• Cadence
• Static Timing Analysis
• Cadence Virtuoso Layout Editor
• Synopsys Tools
• Very-Large-Scale Integration (Vlsi)
• Eldo
• Cadence Virtuoso
• Vhdl
• Field-Programmable Gate Arrays (Fpga)
• Modelsim
• Analog Circuit Design
• Cadence Spectre
• Eda