Deepashree A
Lead Design Engineer at Cadence Design Systems
- Role
- Lead Design Engineer at Cadence
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Deepashree A
RTL Design Engineer.master\'s degree in VLSI design and Embedded systems from BMSCE, Bangalore.currently working at Chipspirit technologies as a RTL Design Engineer.INDUSTRIAL TRAINING1. verilog for design and verification : fundamental concepts of verilog designs with examples like FIFO,TLC, SPI controller, APB protocol etc, 2. System verilog for functional verification :Projects:1. Development of AXI3.0 and validating using AXI slave VIP.2. Memory controller deign verification.3. UVM for functional verification: Basics of UVM constructs with an example of AHB protocol UVC developmentSKILL SET:programming languages : C, C++, embedded Chardware discription languages : VHDL and verilog.hardware simulation software: MATLAB, xilinx, cadence.platforms: windows, Linux.
Experience
Lead Design Engineer
Jan 2025 — Present · Bengaluru, IN
Education
BMS Institute of Technology and Management
Bachelor's degree, Electronics and Communications Engineering
B. M. S. College of Engineering
Master's degree, VLSI design and Embedded systems
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