Deepak Kumar Tiwary
Memory Design Engineer @ BROADCOM Inc | Trainee @ STMicroelectronics |MTech (VLSI Design) | ECU Validation Automotive Industry(HELLA-FORVIA)
- Role
- Memory Design Engineer at Broadcom
- Location
- Bengaluru, KA, IN
- LinkedIn followers
- 500 followers
About Deepak Kumar Tiwary
As a Memory Design Engineer at Broadcom, I apply my skills in digital circuit design…
Experience
Memory Design Engineer
Jul 2024 — Present · Bengaluru, IN
SRAM(2 and 3nm)- SPHD Memory Compiler (MEMCOMP Flow)Understanding of SRAM Bitcell and its characteristics(Ion & Ioff current, Data Retention, Static Noise Margin, Write Margin).Fundamentals of Process Variability and its effect on memory design.ESP Tool for Formal Equivalence Check.ModelOK -Validating the liberty timing and power number while stressing the setup and hold window. PowerupOK- Ensuring that the memory works fine(No Direct path to GND, No Lockup states) during ramping of supplies, random inputs.monte carlo simulation :N instances X PVTs X Strategies
Education
Kendriya Vidyalaya
AISSCE
Visvesvaraya Technological University
Bachelor of Engineering - BE
Amrita Vishwa Vidyapeetham
Master of Technology - MTech
2022 — 2024
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